1. Field of the Invention
This invention generally relates to a germanium (Ge) imaging device and, more particularly, to a Ge optical device fabricated on a glass substrate.
2. Description of the Related Art
There is a great deal of interest in devices fabricated on Ge wafers, including CMOS devices, optical sensors, and imagers. For example, the use a Ge film permits an imager to work in a different spectrum of wavelengths than a silicon-based device. However, due to mismatched lattices and differences in thermal expansion, it is difficult to integrate Ge films into conventional silicon-based integrated circuit (IC) fabrication processes.
Although more costly to manufacture, optical sensing devices can be made on a Ge substrate. Then, the more conventional read-out and drive circuitry can be fabricated in silicon (Si), the Si substrate bonded to the Ge substrate, and the Ge optical sensors electrically connected to the Si substrate read-out circuitry. For handling purposes these substrates are typically relatively thick. However, many Ge-based devices need only be fabricated on thin films, and in some cases a thick Ge substrate degrades Ge device performance.
In U.S. Pat. No. 7,358,107, a germanium film is selectively epitaxially grown on a Si wafer with built-in devices. Although the process is low in cost and it is straight forward to integrate the Ge devices on Si wafer, the integration of the Ge device may affect the Si device characteristics. Another issue with this technology is the Ge film quality. Although the overgrown Ge film quality is much better than the Ge film directly grown on Si, devices fabricated on the overgrown Ge film cannot meet very strict requirements for reverse leakage current performance. PN junction diodes fabricated on selectively epitaxially grown Ge film or overgrown Ge film are well known to exhibit poor reverse leakage.
In U.S. Pat. No. 7,157,300, a germanium wafer is bonded to a Si CMOS wafer and subsequently split. Good quality germanium thin film can be transferred to the Si CMOS wafer using this process. However, the Ge thickness is limited to 2-5 um and electrical connections between the bonded Ge film and the underlying Si CMOS devices are a challenge. The Ge device fabrication is constrained by the completion of Si CMOS prior to the Ge film transfer. For example, the maximum process temperature of the Ge device has to be lower than 400° C. due to the already formed Al interconnects.
In US Patent Publication 2008/0121805, Ge devices are fabricated on a Ge/Si wafer. Then, the Ge devices are flip chip bonded to Si CMOS ICs. In this approach, the Ge film is epitaxially grown on Si wafer. Due to the high mismatch between the Ge and Si lattices, defect-free Ge film on a Si wafer is very difficult to achieve.
A Ge wafer directly bonded to a Si wafer for device fabrication has also been suggested, for example, in U.S. Pat. No. 6,645,831. Initially, a thick Ge wafer is bonded to a Si wafer. Then, a significant amount of the Ge wafer is subsequently removed by polishing and etching. Finally, devices are fabricated in the remaining thin layer of Ge film on Si wafer. Although good quality germanium film can be formed using wafer direct bonding, the large difference in the thermal expansion coefficient between the Si and Ge results in the Ge film cracking or peeling during the device fabrication process.
It would be advantageous if devices could be fabricated on a high quality thin film of Ge and, subsequent to fabrication, electrically connected to circuitry in a Si substrate.